1. Field of the Invention
The present invention relates to an insulated-gate FET (field effect transistor), and more particularly to an insulated-gate FET formed on a semiconductor substrate of an SOI (silicon on insulator) structure.
2. Description of the Related Art
It has been well known that there appears a kink phenomenon in drain voltage-current characteristics of a MOS (metal-oxide semiconductor) FET fabricated on an SOI substrate. The relationship of the drain current versus drain voltage while the gate is kept constant is shown in FIG. 1, where an FET on SOI exhibits an increase in the drain current in comparison with a bulk transistor inherently having no kink. Transistors having the kink phenomenon cause overshoot in the output voltage waveform of a source-follower circuit when a pulse voltage is input to the gate electrode, as shown in FIG. 2.
It has been known that the kink phenomenon does not appear if the semiconductor substrate on the SOI substrate is as thin as approximately 1000 .ANG.. However, the kink phenomenon does appear when the semiconductor substrate is thicker than 3000 .ANG.. For SOI substrate thicknesses between 1000 .ANG. and 3000 .ANG., the kink phenomenon may occur, depending on the operating voltage and the impurity concentration. With a thicker substrate, the voltage at which the kink phenomenon occurs becomes lower (see FIG. 1). Further, the higher the impurity concentration, the more likely it is that the kink phenomenon will occur.
While the kink phenomenon does not appear when a very thin semiconductor substrate is employed, there is a problem in that the manufacture of a semiconductor substrate as thin as 1000 .ANG. on an SOI substrate is very difficult, and accordingly, the production cost is far beyond that of an approximately 1 .mu.m thick semiconductor substrate on an SOI substrate. Therefore, there has been a need to develop a semiconductor device structure which causes no kink phenomenon, even if the semiconductor substrate is approximately 1 .mu.m thick. It is supposed that the kink phenomenon is caused by a part of the semiconductor substrate beneath the channel and in the vicinity of the insulating substrate, which becomes floating so as to cause fluctuation in the potential during operation.
In order to suppress the potential fluctuation of the semiconductor substrate, a contact electrode is provided on a region of the semiconductor substrate extending from the channel, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 52-35922 (published Mar. 9, 1977) and as described below.
FIG. 3(a) is a cross-sectional side view of a main portion of a prior art transistor. FIG. 3(b) is a plan view showing the electrode layout. In FIGS. 3(a) and 3(b), the numeral 1 denotes a supporting substrate; the numeral 2 denotes an insulating layer; the numeral 21 denotes an insulating film; the numeral 3 denotes a semiconductor substrate; the numeral 31 denotes a channel; the numeral 32 denotes a substrate contact; the numeral 4 denotes an element isolation region; the numeral 5 denotes a gate; the numeral 51 denotes a gate insulating oxide film; the numeral 52 denotes an oxide film; the numeral 55 denotes a gate electrode contact; the numeral 6 denotes a source region; the numeral 61 denotes a source contact; the numeral 7 denotes a drain region; and the numeral 71 denotes a drain contact. An SOI substrate is composed of supporting substrate 1, insulating layer 2 and semiconductor substrate 3. As seen in FIG. 3(b), a part of the semiconductor substrate 3 extending from channel 31 which is located beneath gate electrode 5, is provided with a substrate contact 32. Substrate contact 32 is connected to source contact 61 via external wiring, and is typically grounded. This configuration has a disadvantage in that the long distance d (illustrated in FIG. 3(b)) between channel 31 and substrate contact 32 causes an increase in electrical resistance. This is likely to cause fluctuation in the channel potential, and accordingly, the kink phenomenon cannot be completely suppressed. Furthermore, there is a disadvantage in that the provision of the substrate contact 32 requires an additional mask process, as well as an increase in the area occupied by each transistor.